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[Other] rs232

Description: this is a vhdl version of MiniUART implementation
Platform: | Size: 964608 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] yibutongxin

Description: 用VHDL编写的串口异步通信的例子，适于RS232、RS422的通信-err
Platform: | Size: 558080 | Author: 王权 | Hits:

[VHDL-FPGA-Verilog] RS422

Description: 这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试-This is a VHDL development with RS422 communication procedures, in the ALTERA FLEX EPF10K passed the test
Platform: | Size: 1586176 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] Verilog_example

Description: 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。 ，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
Platform: | Size: 1064960 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] 232_transmitter

Description: Rs232 tramslator usage -Rs232 tramslator usage
Platform: | Size: 1024 | Author: wei hi | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[VHDL-FPGA-Verilog] rs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Platform: | Size: 121856 | Author: pp | Hits:

[Com Port] serialrxtx

Description: 个人原创，已经测试通过。功能：完成串行数据与RS232格式数据的收发转换，ST16C450+串并双向转换兼收发时序产生功能，优点：省去了传统的ST16C450需要CPU干预的缺点，简化设计， 纯硬件自动转换，缺点：忽略各种异常报警，适用于误码测试时使用（传输错误由误码测试功能模块完成检测）。-Personal originality, have the test. Function: the completion of serial data and send and receive RS232 data format conversion, ST16C450+ String and two-way conversions and transceivers generate timing features, advantages: eliminating the traditional need for CPU intervention ST16C450 shortcomings, simplify the design, pure hardware automatically converted, disadvantages: ignore the various abnormal alarm, error test applies to the use of (transmission errors by the error detection test function modules completed).
Platform: | Size: 26624 | Author: fg0112 | Hits:

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

Description: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 -杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.
Platform: | Size: 92160 | Author: Wuxinmin | Hits:

[Com Port] uart

Description: 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
Platform: | Size: 6144 | Author: zhangjiansen | Hits:

[SCM] RS485

Description: 用VERILOG语言写的RS485通信程序,经调试可以直接使用-Verilog language used to write the RS485 communication program, the debugger can be used directly
Platform: | Size: 653312 | Author: 李俭 | Hits:

[Software Engineering] RS232_TxD_source_code

Description: RS232 Transmitter VHDL Code
Platform: | Size: 1024 | Author: mohd | Hits:

[VHDL-FPGA-Verilog] uart01

Description: 一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序-A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
Platform: | Size: 140288 | Author: ouping | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[Com Port] rxd

Description: VHDL语言写的UART通信接收端程序，适用于RS232协议-VHDL language the receiving end of the UART communication procedures, applicable to RS232 protocol
Platform: | Size: 2048 | Author: 刘红平 | Hits:

[Com Port] FPGArs232

Description: FPGA中实现rs232串口通信程序，上位机和FPGA互发数据-FPGA to achieve rs232 serial communication procedures, each host computer and FPGA-fat data
Platform: | Size: 100352 | Author: wg | Hits:

[Driver Develop] Rs232_Recv2

Description: controller RS232 for receiving serial data at different speeds
Platform: | Size: 1024 | Author: Natacho | Hits:

[Driver Develop] CameraDriver

Description: This module use OV7620 digital camera on the 24-bit RBG (8:8:8) data and display that in RS232 uart interface
Platform: | Size: 5120 | Author: Joelmir J Lopes | Hits:

[Program doc] async_transmitter

Description: 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
Platform: | Size: 1024 | Author: su | Hits:

[VHDL-FPGA-Verilog] DM7_COLR_LCD_C5T

Description: 任意信号波形采样和频谱分析演示文件 ADC信号采样、RS232串行通信和频谱分析 增加ADC采样控制模块，接上ADC，即可把模拟信号采入PC机上显示，和相应的频谱分析。 -Arbitrary signal waveforms and spectral analysis of the sampling ADC signal sample presentation, RS232 serial communication and increase the ADC sampling frequency spectrum analysis control module, connected to ADC, the analog signal can take into the PC, display, and the corresponding spectral analysis.
Platform: | Size: 41984 | Author: 邢旭 | Hits:
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